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IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER WITH BUS-HOLD AND 5 VOLT TOLERANT I/O
* Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * CMOS power levels (0.4 W typ. static) * All inputs, outputs, and I/O are 5V tolerant * Supports hot insertion * Available in SSOP, TSSOP, and TVSOP packages
IDT74LVCH16276A
FEATURES:
DESCRIPTION:
DRIVE FEATURES: APPLICATIONS:
* High Output Drivers: 24mA * Reduced system switching noise
* 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems
The LVCH16276A synchronous bus exchanger is built using advanced dual metal CMOS technology.The LVCH16276A is a high-speed, bidirectional, 12-bit, registered, bus multiplexer for use in synchronous memory interleaving applications. All registers have a common clock and use a clock enable (CExxx) on each data register to control data sequencing. The output enables and mux select (OEA, OEB and SEL) are also under synchronous control allowing direction changes to be edge triggered events. The tri-port bus exchanger has three 12-bit ports. Data may be transferred between the A port and either/both of the B ports. The clock enable (CE1B, CE2B, CEA1B and CEA2B) inputs control the data storage. Both B ports have a common output enable (OEB) to aid in synchronously loading the B registers from the B port. All pins of the LVCH16276A can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVCH16276A has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The LVCH16276A has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
CEA1B CLK
1
CE
29
A-1B REGISTER D Q 1B-A REGISTER Q D CE
1B1:12
12
CE1B
56
12
SEL OEB OEA A1:12
28 30 27
CONTRO L REGISTER M U X
1
12
12
12
0
CE2B
55
12
12
CE 2B-A REGISTER D Q CE A-2B REGISTER Q D
12
CEA2B
2
2B1:12
12
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4230/2
IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
CEA1B CEA2B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 OEA SEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CE1B CE2B 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 OEB CLK
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM TSTG IOUT IIK IOK ICC ISS Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND -0.5 to +6.5 -65 to +150 -50 to +50 -50 100
Unit V C mA mA mA
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 6.5 6.5 Max. 6 8 8 Unit pF pF pF
NOTE: 1. As applicable to the device type.
SSOP/ TSSOP/ TVSOP TOP VIEW
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IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Signal A(1:12) 1B(1:12) 2B(1:12) CLK CEA1B CEA2B CE1B CE2B SEL OEA OEB I/O I/O I/O I/O I I I I I I I I Description Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.(1) Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.(1) Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.(1) Clock Input. Clock Enable Input for the A-1B Register. If CEA1B is LOW during the rising edge of CLK, data will be clocked into register A-1B (Active LOW). Clock Enable Input for the A-2B Register. If CEA2B is LOW during the rising edge of CLK, data will be clocked into register A-2B (Active LOW). Clock Enable Input for the 1B-A Register. If CE1B is LOW during the rising edge of CLK, data will be clocked into register 1B-A (Active LOW). Clock Enable Input for the 2B-A Register. If CE2B is LOW during the rising edge of CLK, data will be clocked into register 2B-A (Active LOW). 1B or 2B Part Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to A Port. When LOW during the rising edge of CLK, SEL enables data transfer from 2B Port to A Port. Synchronous Output Enable for A Port (Active LOW). Synchronous Output Enable for 1B Port and 2B Port (Active LOW).
NOTE: 1. These pins have "Bus-hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTION TABLES(1)
Inputs 1Bx H L X X X X X 2Bx X X X H L X X SEL H H H L L L X CE1B L L H X X X X CE2B X X X L L H X OEA L L L L L L H CLK Outputs Ax H L A
(2)
Inputs Ax H L H L H L X X X CEA1B L L L L H H H X X CEA2B L L H H L L H X X OEB L L L L L L L H L CLK 1Bx H L H L B(2) B(2) B
(2)
Outputs 2Bx H L B(2) B(2) H L B(2) Z Active
H L A
(2)
Z
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance = LOW-to-HIGH Transition 2. A, B = Output level before the indicated steady-state input conditions were established.
Z Active
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IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC -- -- -- -- -- -- -- -0.7 100 -- -- -- 50 -1.2 -- 10 10 500 A V mV A VCC = 3.6V VO = 0 to 5.5V -- -- 10 A Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VI = 0 to 5.5V Test Conditions Min. 1.7 2 -- -- -- Typ.(1) -- -- -- -- -- Max. -- -- 0.7 0.8 5 A V Unit V
Quiescent Power Supply Current Variation
3.6 VIN 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND
A
NOTES: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. - 75 75 -- -- --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- 500
Unit A A A
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IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 25C
Symbol CPD CPD Parameter Power Dissipation Capacitance per Bus Exchanger Outputs enabled Power Dissipation Capacitance per Bus Exchanger Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical Unit pF
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IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tSU tSU tSU tH tH tH tW tSK(o) Parameter Propagation Delay CLK to 1Bx or CLK to 2Bx Propagation Delay CLK to Ax Output Enable Time CLK to Ax, CLK to 1Bx, or CLK to 2Bx Output Disable Time CLK to Ax, CLK to 1Bx, or CLK to 2Bx Set-Up Time, HIGH or LOW Data to CLK Set-Up Time, OEA to CLK, OEB to CLK Set-Up Time, SEL to CLK Set-Up Time, CEA1B to CLK, CE1B to CLK , CE2B to CLK, or CEA2B to CLK Hold Time, CLK to Data Hold Time, CLK to OEA, CLK to OEB, CLK to SEL Hold Time, CLK to CEA1B, CLK to CE1B, CLK to CE2B, CLK to CEA2B Pulse Width, CLK HIGH Output Skew(2) 1.5 1.5 1.5 1.8 1 1 0.7 2.5 -- -- -- -- -- -- -- -- -- 500 1.5 1.5 1.5 1.8 1 1 0.7 2.5 -- -- -- -- -- -- -- -- -- 500 ns ns ns ns ns ns ns ns ps 1.5 6.6 1.5 6.6 ns SEL stable, CExB Enabled SEL changing, CExB Disabled SEL changing, CExB Enabled 1.5 1.5 1.5 1.5 7 7.5 7.6 6.8 1.5 1.5 1.5 1.5 5.8 6.5 6.6 5.8 ns ns Min. 1.5 Max. 6.6 VCC = 3.3V 0.3V Min. 1.5 Max. 5.7 Unit ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
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IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 Pulse (1, 2) Generator VIN D.U.T. RT 500 CL
LVC Link
VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
VLOAD Open GND
6 2.7 1.5 300 300 50
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
LVC Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VOL+VLZ VOL VOH VOH-VHZ 0V
LVC Link
VOUT
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
VIH VT 0V VOH VT VOL VOH VT VOL tPLH2 tPHL2
LVC Link
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC Link
INPUT
Set-up, Hold, and Release Times
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE VT
LVC Link
tPLH1
tPHL1
OUTPUT 1
VT
tSK (x)
tSK (x)
OUTPUT 2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Pulse Width
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT LVC X XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package
PV PA PF
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package
276A 12-Bit Synchronous Bus Exchanger 16 H 74 Double-Density, 24mA Bus-hold -40C to +85C
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